Welcome to the ECE 270 simulator! This simulator was initially created as a personal project but has since turned into an extremely useful tool for ECE 270 students wishing to avoid late nights in lab working on the physical board. We have since put those dark days behind us.

It came in extremely handy for when the course was forced online during the pandemic, ensuring that students continued to be able to gain experience with Verilog/SystemVerilog in an online environment. We've since returned to in-person classes, but we will continue to use it for the class to help reduce the overall demand for limited physical lab resources.

Starting this semester, we'd like for you to be able to gain a better understanding of how to use this tool, to navigate and utilize it to its full extent, and most importantly, to avoid fatal mistakes. We have therefore designed a tutorial system to teach you how to use the website.

If you are taking this class for the first time, it is essential that you take this tutorial now.

(BTW we're all about shortcuts here! You can use the Left/Right arrow keys to navigate through the tutorial.)

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These are the files stored in your browser's localStorage. Double-click to open one:

File Manager

Columns:    Name    |    Created on    |    Last modified

Create new file/workspace

Select a workspace:

Enter a filename:

Settings

Dark Mode

Simulate-upon-Save

The Ctrl+S shortcut, when used inside the editor, will both save and simulate the code you've written. If you don't want this behavior, flip the slider to disable it.

Change Simulation Type

Disable this if you wish to simulate the original Verilog you've written (source simulation), or enable to simulate the synthesized version of your design (mapped simulation).

Change Evaluation Board Theme

Do you also wonder, like Rick, why the simulator board is blue when the real board is green? Change the color scheme here!

FPGA Communication Terminal

In your lab sessions towards the end of the semester, you will start working on Verilog designs involving the implementation of a simple computer on the FPGA/simulator.

For the last few labs, we would have had you use the UART communication port on the FPGA to add the capability of communicating with your FPGA with the help of a virtual terminal. However, since we're doing this online, we will be using a terminal to communicate with your simulations instead.

The purpose of the communication could be to send commands to the FPGA with the help of the terminal to display things on the LEDs and SS displays, or to read the values of certain registers by outputting them to the terminal. We will have you implement something similar in these last two labs.

Auto-switch to Terminal

If this option is enabled when the simulation starts, the view immediately changes to the terminal. Disable if you want to keep the code in view when the simulation starts.

Your User Profile

Loading profile data... (this can take a while if you've been using the simulator extensively.)

Visits Visits
Simulations Simulations
Demoes Demoes
Errors Errors

(Keep in mind that more errors does not necessarily mean you are doing badly!)

To get the full details of all the errors you have made on the simulator, click here to download the raw JSON data.

To get a ZIP file of all your work, click here.

Workspace Settings for 'workspace'

This panel allows you to configure workspace-specific settings for support modules.

No modules are currently available.